industrial temperature range idt74alvch32374 3.3v cmos 32-bit edge-triggered d-type flip-flop 1 february 2000 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ?2000 integrated device technology, inc. dsc-4909/2 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ?v cc = 2.5v 0.2v ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? available in 96-ball lfbga package functional block diagram drive features: ? high output drivers: 24ma ? suitable for heavy loads applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems idt74alvch32374 3.3v cmos 32-bit edge-triggered d-type flip-flop with 3-state outputs and bus-hold description: this 32-bit edge-triggered d-type flip-flop is built using advanced dual metal cmos technology. this high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. the output enable ( oe ) and clock (clk) controls are organized to operate the device as four 8-bit registers, two 16-bit registers, or one 32-bit register with common clock. flow-through organization of signal pins simplifies layout. all inputs are designed with hysteresis for improved noise margin. the alvch32374 has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. the alvch32374 has ?bus-hold? which retains the inputs? last state whenever the input goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistor. 1 oe d c 1 clk 1 d 1 1 q 1 to seven other channels 3 oe d c 3 clk 3 d 1 3 q 1 to seven other channels 2 oe d c 2 clk 2 d 1 2 q 1 to seven other channels 4 oe d c 4 clk 4 d 1 4 q 1 to seven other channels a3 a4 a5 h3 h4 e5 j3 j4 j5 t3 t4 n5 e2 a2 j2 n2
industrial temperature range 2 idt74alvch32374 3.3v cmos 32-bit edge-triggered d-type flip-flop lfbga topview 96 ball lfbga package attributes pin configuration 1.5mm max. 1.4mm nom. 1.3mm min. 0.8mm 6 5 4 3 2 1 top view abcdefghjklmnprt abcdefghjklmnprt 6 5 4 3 2 1 13.5mm 5.5mm ab c e f gh j k lmn p d t r 6 5 4 3 2 1 1 d 6 1 d 8 2 d 1 2 d 22 d 4 2 d 8 2 oe 1 d 4 1 d 5 1 d 7 2 d 6 2 d 7 2 d 3 2 d 5 1 d 2 1 d 3 1 d 1 gnd 3 d 8 3 d 2 3 d 4 4 d 1 4 d 3 4 d 2 3 d 3 3 d 5 4 d 4 3 d 1 4 d 6 gnd gnd 1 q 1 v cc gnd v cc 1 q 2 1 q 3 4 q 6 4 q 8 gnd gnd 2 q 2 2 q 4 1 q 4 1 q 5 1 q 7 2 q 6 2 q 7 3 q 7 4 q 2 3 q 3 3 q 5 4 q 4 3 q 1 1 q 6 1 q 8 2 q 1 2 q 8 2 q 3 2 q 5 3 q 6 3 q 8 3 q 2 3 q 4 4 q 1 4 q 3 gnd v cc gnd v cc gnd gnd v cc gnd gnd v cc gnd v cc 3 d 7 3 d 6 1 oe 1 clk 3 clk 4 d 54 d 8 4 d 7 4 oe 4 q 7 4 q 5 v cc gnd gnd 3 oe 2 clk gnd 4 clk
industrial temperature range idt74alvch32374 3.3v cmos 32-bit edge-triggered d-type flip-flop 3 pin names description x d x data inputs (1) xclk clock inputs x q x 3-state outputs xoe 3-state output enable inputs (active low) pin description symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, 50 ma v i < 0 or v i > v cc i ok continuous clamp current, v o < 0 ?50 ma i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . note: 1. these pins have "bus-hold". all other pins are standard inputs, outputs, or i/os. function table (each flip-flop) (1) notes: 1. h = high voltage level l = low voltage level x = don?t care z = high impedance = low-to-high transition 2. output level of q before the indicated steady-state conditions were established. inputs outputs x oe xclk xdx xqx l hh l ll l h or l x q (2) hx x z note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 5 7 pf c out output capacitance v out = 0v 7 9 pf c i/o i/o port capacitance v in = 0v 7 9 pf capacitance (t a = +25c, f = 1.0mhz)
industrial temperature range 4 idt74alvch32374 3.3v cmos 32-bit edge-triggered d-type flip-flop symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input high current v cc = 3.6v v i = v cc ?? 5a i il input low current v cc = 3.6v v i = gnd ? ? 5a i ozh high impedance output current v cc = 3.6v v o = v cc ?? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v ? 0.1 40 a i cch v in = gnd or v cc i ccz ? i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 750 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c note: 1. typical values are at v cc = 3.3v, +25c ambient. bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? 45 ? ? a i bhl v i = 0.7v 45 ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range idt74alvch32374 3.3v cmos 32-bit edge-triggered d-type flip-flop 5 operating characteristics, t a = 25c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 62 60 pf c pd power dissipation capacitance outputs disabled 32 36 notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2 skew between any two outputs of the same package and switching in the same direction. switching characteristics (1) v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit f max 150 ? 150 ? 150 ? m h z t plh propagation delay 1 5.3 ? 4.9 1 4.2 ns t phl xclk to xqx t pzh output enable time 1 6.2 ? 5.9 1 4.8 ns t pzl xoe to xqx t phz output disable time 1 5.3 ? 4.7 1.2 4.3 ns t plz xoe to xqx t su setup time, data before clk 2.1 ? 2.2 ? 1.9 ? ns t h hold time, data after clk 0.6 ? 0.5 ? 0.5 ? ns t w pulse duration, clk high or low 3.3 ? 3.3 ? 3.3 ? ns t sk(o) output skew (2) ? ????500ps note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3v i ol = 24ma ? 0.55
industrial temperature range 6 idt74alvch32374 3.3v cmos 32-bit edge-triggered d-type flip-flop open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz alvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 1.0mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range idt74alvch32374 3.3v cmos 32-bit edge-triggered d-type flip-flop 7 ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx alvc xxxx xx package device type temp. range bf bfg 32 74 low-profile fine pitch ball grid array lfbga - green 32-bit edge triggered d-type flip-flop with 3-state outputs -40c to +85c xxx family bus-hold 374 bus-hold 32-bit bus density, 24ma h
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